FIG. 1 is a cross-sectional view of a portion of a prior art insulated gate turn-off (IGTO) thyristor 10 described in the inventor's U.S. Pat. Nos. 7,705,368 and 9,306,598, incorporated herein by reference. An npnp semiconductor layered structure is formed. A pnp transistor is formed by a p+ substrate 12 (emitter), an n-epitaxial (epi) layer 14 (base), and a p− well 16 (collector). The p-well 16 is typically formed using implantation and drive-in. There is also an npn transistor formed by the n-epi layer 14 (collector), the p-well 16 (base), and an n+ layer 18 (emitter). A bottom anode electrode 20 contacts the substrate 12, and a top cathode electrode 22 contacts the n+ layer 18. Trenches 24, coated with an oxide layer 25, contain a conductive gate 26 (forming interconnected vertical gate regions) which is contacted by a gate electrode 28. The p-well 16 surrounds the gate structure and, outside the drawing, the n− epi layer 14 extends to the surface around the p-well 16 near a termination area.
When the anode electrode 20 is forward biased with respect to the cathode electrode 22, but without a sufficiently positive gate bias, there is no current flow, since there is a reverse biased pn junction and the product of the betas (gains) of the pnp and npn transistors is less than one.
When there is a sufficient positive voltage applied to the gate 26, and there is a forward anode-cathode voltage, electrons from the n+ layer 18 become the majority carriers along the trench sidewalls and below the bottom of the trenches 24 in an inversion layer. This inversion layer forms a voltage-induced emitter, resulting in the effective width of the npn base (the portion of the p-well 16 below the trenches 24) to be reduced. As a result, the beta of the npn transistor increases to cause the product of the betas to exceed one. This condition results in “breakover,” when holes are injected into the lightly doped n-epi layer 14 and electrons are injected into the p-well 16 to fully turn on the thyristor. This behavior results in the controlled latch-up of the device involving regenerative action. Accordingly, the gate bias initiates the turn-on, and the full turn on is accomplished by the current flow through the npn and pnp transistors.
The voltage applied to the gate needed to turn on the device is called the gate turn on, or threshold, voltage Vt. A typical threshold voltage Vt may be around 5 volts.
When the gate bias is made zero or negative volts, the thyristor turns off.
Although not described in U.S. Pat. No. 7,705,368, the identical gate and cathode structure shown in FIG. 1 may be repeated as an array (or matrix) of cells across the thyristor, and the various components may be connected in parallel so each cell conducts a small portion of the total current.
Such IGTO thyristors have a relatively high current density when on. In contrast, insulated gate bipolar transistors (IGBTs) generally have a lower current density when on. Accordingly, for at least high current applications, IGTO thyristors are preferred.
When the device is on, typically a zero or negative voltage can be applied to the gate to turn it off (assuming the anode and cathode are still forward biased). If the anode-cathode voltage differential is above a certain value, the device cannot be turned off by the gate. This value is called the maximum turn off voltage, and is specified at a particular current, such as 20A. The device can be damaged if the maximum turn off voltage is exceeded. The maximum turn off voltage is usually specified by the manufacturer.
Additionally, even when there is no gate turn on voltage, free electrons under a high anode-cathode voltage can undesirably turn the device on. The maximum forward voltage that can be applied to the device prior to switching without a gate turn on voltage is called the forward breakover voltage. It is desirable that this breakover voltage be high, such as equal to the breakdown voltage. Exceeding the breakover voltage may damage the device.
What is needed is an improvement of the general type of IGTO thyristor shown in FIG. 1, where the gate turn on voltage and other IGTO thyristor parameters can be adjusted independently, while not adversely affecting the maximum turn off voltage or decreasing the breakover voltage. Ideally, the safe operating area (SOA) is improved, where the SOA is defined as the voltage and current conditions over which the device can be expected to operate without self-damage.